Volume 16, Issue 2June 2023Current IssueIssue-in-Progress
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research-article
Open Access
Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis
Article No.: 17, pp 1–25https://doi.org/10.1145/3559543

Recent efforts for improving the performance of neural network (NN) accelerators that meet today’s application requirements have given rise to a new trend of logic-based NN inference relying on fixed function combinational logic. Mapping such large ...

research-article
FPGA Acceleration of Probabilistic Sentential Decision Diagrams with High-level Synthesis
Article No.: 18, pp 1–22https://doi.org/10.1145/3561514

Probabilistic Sentential Decision Diagrams (PSDDs) provide efficient methods for modeling and reasoning with probability distributions in the presence of massive logical constraints. PSDDs can also be synthesized from graphical models such as Bayesian ...

research-article
Open Access
Hardware-accelerated Real-time Drift-awareness for Robust Deep Learning on Wireless RF Data
Article No.: 19, pp 1–29https://doi.org/10.1145/3563394

Proactive and intelligent management of network resource utilization (RU) using deep learning (DL) can significantly improve the efficiency and performance of the next generation of wireless networks. However, variations in wireless RU are often affected ...

research-article
Open Access
A Survey on FPGA Cybersecurity Design Strategies
Article No.: 20, pp 1–33https://doi.org/10.1145/3561515

This article presents a critical literature review on the security aspects of field-programmable gate array (FPGA) devices. FPGA devices present unique challenges to cybersecurity through their reconfigurable nature. The article also pays special ...

research-article
Open Access
Automatic Creation of High-bandwidth Memory Architectures from Domain-specific Languages: The Case of Computational Fluid Dynamics
Article No.: 21, pp 1–34https://doi.org/10.1145/3563553

Numerical simulations can help solve complex problems. Most of these algorithms are massively parallel and thus good candidates for FPGA acceleration thanks to spatial parallelism. Modern FPGA devices can leverage high-bandwidth memory technologies, but ...

research-article
Hardware Optimizations of Fruit-80 Stream Cipher: Smaller than Grain
Article No.: 22, pp 1–32https://doi.org/10.1145/3569455

Fruit-80, which emerged as an ultra-lightweight stream cipher with 80-bit secret key, is oriented toward resource-constrained devices in the Internet of Things. In this article, we propose area and speed optimization architectures of Fruit-80 on FPGAs. ...

research-article
Open Access
FlexCNN: An End-to-end Framework for Composing CNN Accelerators on FPGA
Article No.: 23, pp 1–32https://doi.org/10.1145/3570928

With reduced data reuse and parallelism, recent convolutional neural networks (CNNs) create new challenges for FPGA acceleration. Systolic arrays (SAs) are efficient, scalable architectures for convolutional layers, but without proper optimizations, their ...

research-article
Open Access
Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-switched Inter-FPGA Networks
Article No.: 24, pp 1–27https://doi.org/10.1145/3576200

While FPGA accelerator boards and their respective high-level design tools are maturing, there is still a lack of multi-FPGA applications, libraries, and not least, benchmarks and reference implementations towards sustained HPC usage of these devices. As ...

research-article
Open Access
VCSN: Virtual Circuit-Switching Network for Flexible and Simple-to-Operate Communication in HPC FPGA Cluster
Article No.: 25, pp 1–32https://doi.org/10.1145/3579848

FPGA clusters promise to play a critical role in high-performance computing (HPC) systems in the near future due to their flexibility and high power efficiency. The operation of large-scale general-purpose FPGA clusters on which multiple users run diverse ...

research-article
Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains
Article No.: 26, pp 1–28https://doi.org/10.1145/3558394

To effectively minimize static power for a wide range of applications, power domains for coarse-grained reconfigurable array (CGRA) architectures need to be more fine-grained than those found in a typical application-specific integrated circuit. However, ...

research-article
Adaptive Selection and Clustering of Partial Reconfiguration Modules for Modern FPGA Design Flow
Article No.: 27, pp 1–24https://doi.org/10.1145/3567427

Dynamic Partially Reconfiguration (DPR) on FPGA has attracted significant research interest in recent years since it provides benefits such as reduced area and flexible functionality. However, due to the lack of supporting synthesis tools in the current ...

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